Position: Senior Physical Design / STA Engineer
Work Location: San Diego, CA (onsite near MCAS Miramar)
Full-time: Salary + Benefits + Bonuses or Contractor
Work Status: US Citizen or US Permanent Resident

Responsibilities:

• Responsible for overseeing all aspects of STA, Physical Design, Sign-Off and Automation in hierarchical and flat SoC designs
• Responsible for Static Timing Analysis and fixing for blocks and/or top level
• Responsible for creating workable digital flows in latest technology nodes (<= 7nm)
• Responsible for automating various aspects of existing or new design flows, including partitioning, floorplanning, placement of blocks and macros, pin placement, power busing, custom routing, CTS, buffer insertion.

Qualifications:

• BSEE required, MSEE preferred
• Excellent knowledge/experience using STA tools and methodology.
• Deep understanding of Liberty files (such as NLDM, CCS and LVF)
• Good software skills and direct experience with Python and Tcl
• Knowledge of Verilog, SystemVerilog, VHDL.
• Very good working knowledge of top level and block physical design for complex chips (10M+ gates) at 7nm or below, using Synopsys ICC or Cadence SOC Encounter
• Hands-on experience executing floorplanning, physical synthesis, CTS, routing, STA with Primetime, power analysis, DRC/LVS, noise analysis
• Experience with multi voltage domains and low power flow
• Good understanding of RTL design and the RTL integration and implementation flow
• Knowledge of Asynchronous design is a BIG plus

If you are hired into a California work location, the anticipated compensation for the position is between $130,000.00 - $170,000.00 and based on a full-time schedule.
Your ultimate compensation may vary as we carefully consider a wide range of factors, including customer assignment, your job-related skills, qualifications, experience and location.